Raised photodiode sensor to increase fill factor and quantum efficiency in scaled pixels

ABSTRACT

An image pixel cell with a doped, hydrogenated amorphous silicon photosensor, raised above the surface of a substrate is provided. Methods of forming the raised photosensor are also disclosed. Raising the photosensor increases the fill factor and the quantum efficiency of the pixel cell. Utilizing hydrogenated amorphous silicon decreases the leakage and barrier problems of conventional photosensors, thereby increasing the quantum efficiency of the pixel cell. Moreover, the doping of the photodiode with inert implants like fluorine or deuterium further decreases leakage of charge carriers and mitigates undesirable hysteresis effects.

FIELD OF THE INVENTION

The present invention relates generally to digital image sensors andmethods of fabrication thereof and in particular to photosensors used ina pixel sensor cell.

BACKGROUND OF THE INVENTION

Typically, a digital imager array includes a focal plane array of pixelcells, each one of the cells including a photosensor, e.g. a photogate,photoconductor, or a photodiode. In a CMOS imager a readout circuit isconnected to each pixel cell which typically includes a source followeroutput transistor. The photosensor converts photons to electrons whichare typically transferred to a floating diffusion region connected tothe gate of the source follower output transistor. A charge transferdevice (e.g., transistor) can be included for transferring charge fromthe photosensor to the floating diffusion region. In addition, suchimager cells typically have a transistor for resetting the floatingdiffusion region to a predetermined charge level prior to chargetransference. The output of the source follower transistor is gated asan output signal by a row select transistor.

Exemplary CMOS imaging circuits, processing steps thereof, and detaileddescriptions of the functions of various CMOS elements of an imagingcircuit are described, for example, in U.S. Pat. No. 6,140,630, U.S.Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652,U.S. Pat. No. 6,204,524, and U.S. Pat. No. 6,333,205, each assigned toMicron Technology, Inc. The disclosures of each of the forgoing patentsare hereby incorporated by reference in their entirety.

In a digital CMOS imager, when incident light strikes the surface of aphotodiode photosensor, electron/hole pairs are generated in the p-njunction of the photodiode. The generated electrons are collected in then-type region of the photodiode. The photo charge moves from the initialcharge accumulation region to the floating diffusion region or thecharge may be transferred to the floating diffusion region via atransfer transistor. The charge at the floating diffusion region istypically converted to a pixel output voltage by a source followertransistor.

Conventional CMOS imagers typically have difficulty transferring all ofthe photogenerated charge from the photodiode to the floating diffusionregion. One problem with transferring charge occurs when the n-typesilicon layer of the photodiode is located close to the surface; thiscauses electron/carrier recombination due to surface defects. There is aneed to reduce this electron/carrier recombination to achieve goodcharge transfer to the floating diffusion region. Another obstaclehindering “complete” charge transference includes potential barriersthat exist at the gate of a transfer transistor.

Additionally, conventional CMOS imager designs provide onlyapproximately a fifty percent fill factor, meaning only half of thepixel is utilized in converting light to charge carriers. As shown inFIG. 1, a top plan view of a conventional CMOS pixel sensor cell, only asmall portion of the cell comprises a photosensor (photodiode) 49. Theremainder of the cell includes the floating diffusion region 14, coupledto a transfer gate 18, and source/drain regions 55 for reset, sourcefollower, and row select transistors having respective gates 19, 24, and25. It is desirable to increase the fill factor of the conventionalcell.

Digital imagers may utilize a pixel containing a p-n-p photodiode 49 asthe photo-conversion device. An example of this design is shown in FIG.2, a cross-sectional view of the pixel of FIG. 1, taken along line A-A′.The pixel sensor cell shown in FIG. 2 has a p-type substrate 60 with ap-well 61. In the illustrated example, a p-type region 10 of photodiode49 is located closest to the surface of substrate 60 and an n-typeregion 12 is buried between the p-type region 10. The p-n-p photodiode49 has some drawbacks. First, there can be a lag problem since the pixeluses a transfer transistor 18 for transferring charge to the floatingdiffusion region 14. Lag occurs because during integration the electroncarriers are collected in the sandwiched n-type region 12 and thentransferred to the floating diffusion region 14 through a transfer gate18. In order to fully utilize the generated electron carrier, it isnecessary to eliminate two energy barriers to reach the floatingdiffusion region 14 (i.e., there is one barrier between the photodiode49 and the transfer gate 18 and another barrier between the transfergate 18 and floating diffusion region 14). Next, charge leakage isanother problem associated with the conventional p-n-p photodiode 49.One source of such leakage occurs when the transfer transistor 18 gatelength is too short, causing sub-threshold current to becomesignificantly high due to charge breakdown between n-type regions onboth sides of the transfer gate channel.

Additionally, as the total area of pixels continues to decrease (due todesired scaling), it becomes increasingly important to create highsensitivity photosensors that utilize a minimum amount of surface area.Raised photodiodes have been proposed as a way to increase the fillfactor and optimize the sensitivity of the CMOS pixel by increasing thesensing area of the cell without increasing the surface area of thesubstrate. Further, raising the photodiode increases the quantumefficiency of the cell by bringing the sensing region closer to themicrolens. However, raised photodiodes, such as described in U.S.application Ser. No. 10/443,891, assigned to Micron Technology, Inc.,and incorporated herein by reference, also have problems with leakagecurrent across the elevated p-n junctions. Accordingly, a raisedphotosensor that reduces this leakage, while increasing the quantumefficiency of the pixel cell, is desired.

SUMMARY OF THE INVENTION

The present invention provides embodiments of image pixel cells with adoped, hydrogenated amorphous silicon photosensor, raised above thesurface of a substrate. Methods of forming the raised photosensor arealso disclosed. Raising the photosensor increases the fill factor andthe quantum efficiency of the pixel cell. Utilizing hydrogenatedamorphous silicon decreases the leakage and barrier problems ofconventional photosensors, thereby increasing the quantum efficiency ofthe pixel cell. Moreover, the doping of the photodiode with inertimplants like fluorine or deuterium further decreases leakage of chargecarriers and mitigates undesirable hysteresis effects.

Additional features and advantages of the present invention will beapparent from the following detailed description and drawings whichillustrate exemplary embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top plan view of a conventional CMOS pixel cell;

FIG. 2 is a cross-sectional view of the pixel cell of FIG. 1, takenalong line A-A′;

FIG. 3 is a top plan view of a pixel cell constructed in accordance withan exemplary embodiment of the invention;

FIG. 4 is a cross-sectional view of the exemplary pixel cell of FIG. 3,taken along line B-B′;

FIG. 5A is a cross-sectional view of the exemplary pixel cell of FIG. 4during an initial stage of processing performed in accordance with theinvention;

FIG. 5B shows the exemplary pixel cell of FIG. 4 at a stage ofprocessing subsequent to that shown in FIG. 5A;

FIG. 5C shows the exemplary pixel cell of FIG. 4 at a stage ofprocessing subsequent to that shown in FIG. 5B;

FIG. 5D shows the exemplary pixel cell of FIG. 4 at a stage ofprocessing subsequent to that shown in FIG. 5C;

FIG. 6 shows an exemplary pixel cell constructed in accordance with asecond embodiment of the invention during a stage of processing.

FIG. 7 shows the exemplary pixel cell of FIG. 6 at a stage of processingsubsequent to that shown in FIG. 6.

FIG. 8 is a block diagram of a CMOS imager chip having an array of pixelsensor cells constructed in accordance with the present invention; and

FIG. 9 is a schematic diagram of a processing system employing a CMOSimager having elevated photodiodes constructed in accordance with thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof and show by way ofillustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical, and electrical changes may be made withoutdeparting from the spirit and scope of the present invention. Theprogression of processing steps described is exemplary of embodiments ofthe invention; however, the sequence of steps is not limited to that setforth herein and may be changed as is known in the art, with theexception of steps necessarily occurring in a certain order.

The terms “wafer” and “substrate,” as used herein, are to be understoodas including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire(SOS) technology, doped and undoped semiconductors, and othersemiconductor structures. Furthermore, when reference is made to a“wafer” or “substrate” in the following description, previous processingsteps may have been utilized to form regions, junctions, or materiallayers in or over the base semiconductor structure or foundation. Inaddition, the semiconductor need not be silicon-based, but could bebased on silicon-germanium, germanium, gallium arsenide or othersemiconductors.

The term “pixel,” as used herein, refers to a photo-element unit cellcontaining a photosensor and associated transistors for convertingphotons to an electrical signal. For purposes of illustration, a singlerepresentative pixel and its manner of formation is illustrated in thefigures and description herein; however, typically fabrication of aplurality of like pixels proceeds simultaneously. Accordingly, thefollowing detailed description is not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims.

In the following description, the invention is described in relation toa CMOS imager for convenience purposes only; the invention, however, haswider applicability to any photosensor of any imager cell. Now referringto the figures, where like numerals designate like elements, FIG. 3illustrates a pixel sensor cell 100 constructed in accordance with afirst exemplary embodiment of the invention. From the top plan view ofthe pixel cell 100, only the raised photodiode region 122 and the cellinsulation region 140 can be seen. The fill factor of the cell 100 isnearly 100 percent, as the photo-sensing region covers the entiresurface area of the cell. Although FIG. 3 shows the invention raisedphotodiode region 122 as covering the entire pixel, the raisedphoto-sensing region of the present invention could have a smallersurface area and could cover much less of pixel sensor cell 100. Alsoshown in FIG. 3 is an insulating layer 140 surrounding the raisedphotodiode so as to insulate each pixel cell 100 from one another.Alternatively, isolation trenches or regions (not shown) are formed inthe raised photodiode region 122 to provide isolation of the raisedphotodiode 122 of a pixel cell 100 from raised portions of adjacentcells.

FIG. 4 illustrates a cross-sectional view of the exemplary pixel sensorcell 100, taken along line B-B′ of FIG. 3. A photosensor 102 having adoped region 103 is formed in a substrate 101. The photosensor 102 is aphotodiode and may be a pinned p-n-p, n-p-n, p-n or n-p junctionphotodiode, a Schottky photodiode, or any other suitable photodiode. Forexemplary purposes only, the illustrated photodiode 102, is a n-pphotodiode, and substrate 101 is illustrated as a p-type substrate.

FIG. 4 also illustrates a floating diffusion region 110 and shallowtrench isolation (STI) 105 in the substrate 101. A drain region 126 isalso formed in the substrate 101. Other structures of pixel cell 100include a transfer transistor gate 106. Reset transistor 120 comprises asimilar gatestack as that of the transfer transistor 106. For claritypurposes, other transistors such as source follower transistor 127 and arow select transistor 129 are represented in electrical schematic formwith the output of the row select transistor 129 being connected to acolumn line 125. The pixel cell 100 can be implemented as a 4 Tconfiguration or in a design with either a higher or lower number oftransistors (e.g., 3 T, 5 T, 6 T).

As shown in FIG. 4, substrate 101 has a first surface level 118. Anepitaxial layer 115 is grown from the top of this first surface level118 to a second surface level 119. Above the epitaxial layer 115 is ahydrogenated amorphous silicon layer 116. An additional hydrogenatedamorphous silicon layer 117 may also be utilized if desired. Inaccordance with the invention, the term “hydrogenated amorphous silicon”means either conventional hydrogenated amorphous silicon (representeda-Si:H) or deuterated amorphous silicon (represented a-Si:D), havingdeuterium substituted for hydrogen, as discussed in more detail below.

The epitaxial layer 115 and the hydrogenated amorphous silicon layer 116are doped such that the layers have opposite doping types to create ap-n junction above the surface level 118 of the substrate. This creates,in effect, an elevated photodiode 122. In this illustration, theepitaxial layer is doped p-type, creating a p-n junction with the n-typesurface region 103. Thus, the hydrogenated amorphous silicon layer 116would be doped n-type. There are several advantages of having aphotodiode 122 constructed in accordance with the invention.

Elevating the photodiode 122 above the surface 118 of the substrate 101makes a much larger surface area available for exposure to light. Forinstance, FIG. 1 shows that in a conventional pixel cell only thephotodiode 49 is exposed to light and useful for generating charge. Asdiscussed above the pixel cell of FIG. 1 has approximately a fiftypercent fill factor. As shown in FIG. 3, the present invention allowsfor a higher fill factor by elevating the photodiode 122 above thesurface level 118 to increase the sensing surface area of the cell 100.Raising the photodiode 122 also increases the quantum efficiency of thecell 100, as the light-sensing portion (the photodiode) 122 is movedcloser to the lens (not shown). The use of hydrogenated amorphoussilicon in the photodiode decreases the leakage current compared withthe traditional leakage effect seen when amorphous silicon is used.

Furthermore, implanting inert species like fluorine or deuterium in thehydrogenated amorphous silicon layer 116 provides additional benefit. Ithas been shown that fluorine implants in hydrogenated amorphous siliconreduce leakage in the silicon by up to five orders of magnitude bybreaking silicon-silicon bonds during the ion implementation. See, forexample, Shannon et al., “Electronic Effects of Light Ion Damage inHydrogenated Amorphous Silicon,” Solid State Electronics vol. 47, p.1903 (2003), incorporated herein by reference. Similarly, deuteratedamorphous silicon (a-Si:D) shows better leakage properties due toreduced trap sites and better passivation.

FIG. 5A shows an exemplary pixel of the present invention at an initialstage of fabrication. In a p-type substrate 101, a separate p-well 131is formed therein. As known in the art, multiple high energy implantsmay be used to tailor the profile and position of the p-type well 131;typically, the p-well region 131 will have a higher dopant concentrationthan the p-type substrate 101. A floating diffusion region 110 is formedin the p-well 131, and is doped n-type in this embodiment.

Isolation regions 105 are etched into the surface of the substrate 101,by any suitable method or technique, and are filled with an insulatingmaterial to form an STI isolation region. The isolation regions may beformed either before or after formation of the p-well 131. A photodiode102 is formed, in this embodiment, by creating a n-type region 103 inthe p-type substrate 101. Photodiode 102 is not, however, limited to ann-p design and may be any type of photosensor as discussed herein.

Also shown in FIG. 5A, a transfer transistor gate 106 and a resettransistor gate 120 are formed at the surface of the substrate betweenthe photodiode 102 and floating diffusion region 110. The transfer andreset transistor gates 106, 120 comprise an insulating or oxide layer109 over a conductive layer 108 formed over a gate oxide layer 107 atthe surface of the substrate 101. Preferably, the conductive layer 108comprises a silicide or silicide/metal alloy. These layers 107, 108, 109may, however, be formed of any suitable material using any suitablemethod, and do not in any way limit the scope of this invention.Completion of the transistor gates 106, 120 includes the addition ofoxide spacers 112 on at least one side of the transistor gatestack. Thespacers 112 may be formed of any suitable material, including, but notlimited to silicon dioxide. As desired, other transistor gates (depictedin FIG. 4) may be erected simultaneously with transfer transistor gate106 and reset transistor gate 120 during this step in the formation, andmay or may not contain the same layer combinations as these gate stacks.

Referring now to FIG. 5B, a selective epitaxial layer 115 is grown nearthe surface of the substrate 101, over the photodiode 102 and adjacentthe sidewall 112 of the transfer transistor gate 106. The epitaxiallayer 115 is grown over this selected region using a hard mask, forexample, a nitride film, to cover other regions of the substrate such asthe floating diffusion region 110. By performing a chemical vapordeposition process, the epitaxial layer 115 may be formed using anysuitable precursor (e.g., silicon tetrachloride, silane, anddichlorosilane). In addition, the epitaxial layer 115 can be doped aseither n-type or p-type by the addition of a suitable dopant gas intothe deposition reactants. In this embodiment, the epitaxial layer 115 isdoped p-type, to create a p-n junction at the intersection of theepitaxial layer 115 with the surface layer 103. The epitaxial layer 115is planarized using chemical mechanical polishing (CMP) to a height ofabout 500-1000 Angstroms above the surface of the substrate. An oxidecap 114 may be used to cover gate stacks to act as a CMP stop.

Subsequently, as shown in FIG. SC, a buffer layer 130 (e.g., TEOS orBPSG) is deposited over the entire substrate 101. An opening 128 is thenpatterned in the layer 130 paralleling the photodiode 102 in thesubstrate 101.

Referring now to FIG. 5D, hydrogenated amorphous silicon is deposited tofill the opening 128 and to cover the buffer layer 130, creating araised layer 116. The layer 116 is then planarized to a thickness ofabout 500-1000 Angstroms. A second hydrogenated amorphous silicon layer117 may be deposited on top of layer 116. Oppositely doping these layers116, 117, respectively p-type and n-type, will create an additional p/njunction raised above the photodiode 102. Alternatively, the twoamorphous silicon layers 116, 117 may be doped the same type (eithern-type or p-type depending on the dopant used for the surface region 103and epitaxial region 115) as to create effectively one layer. Theconcentration levels of dopants may be similar to that of a conventionalphotodiode. A preferable concentration for the top layer 117 is betweenabout 1.0 e²⁰ to about 5.0 e¹⁷, about 1.0 e¹⁷ to about 5.0 e¹⁶ for thefirst amorphous silicon layer 116, and about 1.0 e¹⁶ to about 5.0 e¹⁵for the epitaxial layer 115. (All concentrations given in units of atomsper cm³).

Next, the amorphous silicon layers 116, 117 are implanted with eitherfluorine ions or deuterium. The fluorine ions may be implanted using anysuitable fluorinated gas (e.g., SiF₂). The implantation of fluorine maybe followed by an annealing step. The deuterated amorphous silicon canbe formed by utilizing a trideuterioammonia (ND3) anneal. The deuteriumreplaces existing hydrogen atoms in the hydrogenated amorphous siliconbonds, according to the following equation: Si—H+D₂=Si-D+HD. Usingconventional masking techniques, the amorphous silicon layers 116, 117can be patterned as desired.

At this stage, the formation of the exemplary pixel sensor cell 100(FIG. 4) is essentially complete. Additional processing steps may beused to form insulating, shielding, and metallization layers as desired.For example, an inter-level dielectric (ILD) such as insulating layer140 (FIG. 3) may be formed in order to provide adequate insulationbetween metallized layers as well as to isolate the amorphous siliconlayers 116, 117 of a pixel cell 100 from adjacent pixel cells. Becausean increased percentage of each pixel sensor cell is covered byphoto-sensing material in accordance with this invention, transparentmetallization layers may be used, so that light is not blocked for thephotosensor. Conventional layers of conductors and insulators (notshown) may also be used to interconnect the structures and to connectthe pixel to peripheral circuitry.

FIGS. 6 and 7 illustrate a second exemplary embodiment of the currentinvention. The process steps for forming the exemplary pixel cell 200are similar to the process shown in FIGS. 5A-5D, with the followingexceptions. As shown in FIG. 6, the epitaxial layer comprises twoenumerated regions 115, 215, as the epitaxial layer is grown not onlyover the photodiode region 102 of the substrate, but also over thefloating diffusion region 110 and the drain region 136 for the resettransistor 120. The epitaxial layer 115 corresponds to the epitaxiallayer 115 described with reference to FIGS. 4-5D. Epitaxial layer 215 isformed just as layer 115 but over the floating diffusion 110 and drainregion 136 for the reset transistor 120. As explained above, thisselective growth can be accomplished using any suitable maskingtechnique. This growth effectively creates an elevated source/drainregion 215 for the reset transistor 120. Accordingly, the drain region136 in the substrate 101 has a shallower junction depth into p-well 131.As before, the epitaxial layer 115 above the photodiode region 102 isdoped p-type if surface region 103 is doped n-type. The epitaxial layer215 is doped n-type, preferably n+ doped. Source/drain region 136 isillustratively n-LDD (n-type lightly doped drain region) in thisembodiment.

FIG. 7 shows completion of the second exemplary pixel cell 200 from thefabrication stage shown in FIG. 6. A suitable buffer layer 130 isdeposited and patterned to create an opening in the buffer layer 130above the epitaxial growth 115. A first hydrogenated amorphous siliconlayer 116 is formed in the opening and over the buffer layer 130. Asecond hydrogenated amorphous silicon layer 117 is formed above thefirst layer 116. Epitaxial layers 116 and 117 are doped either n-orp-type depending on the doping profile of the substrate 101 andepitaxial layer 115. Finally, as discussed above, either deuterium orfluorine is implanted into layers 116 and 117 in order to decreasecharge leakage across these layers.

The invention as described and illustrated above utilizes a silicon typesubstrate 101. Alternatively, the invention may be implemented as a SOI(silicon on insulator) design, utilizing any suitable insulating layersandwiched between the substrate and an additional silicon layer. Theother wafer structures discussed previously, such as SOS and germaniumsubstrates, may also be used.

FIG. 8 illustrates a block diagram of an exemplary CMOS imager 308having a pixel array 204 with each pixel cell being constructed as inone of the embodiments described above. Pixel array 204 comprises aplurality of pixels arranged in a predetermined number of columns androws (not shown), attached to the array 204 is signal processingcircuitry, as described herein, at least part of which may be formed inthe substrate. The pixels of each row in array 204 are all turned on atthe same time by a row select line, and the pixels of each column areselectively output by respective column select lines. A plurality of rowand column lines are provided for the entire array 204. The row linesare selectively activated by a row driver 210 in response to row addressdecoder 220. The column select lines are selectively activated by acolumn driver 260 in response to column address decoder 270. Thus, a rowand column address is provided for each pixel. The CMOS imager isoperated by the timing and control circuit 250, which controls addressdecoders 220, 270 for selecting the appropriate row and column lines forpixel readout. The control circuit 250 also controls the row and columndriver circuitry 210, 260 such that these apply driving voltages to thedrive transistors of the selected row and column lines. The pixel columnsignals, which typically include a pixel reset signal (V_(rst)) and apixel image signal (V_(sig)), are read by a sample and hold circuit 261associated with the column device 260. V_(rst) is read from a pixelimmediately after the floating diffusion region 110 is reset out by thereset gate 120; V_(sig) represents the charges transferred by thetransfer gate 106, from the photodiode regions 103, 122 to the floatingdiffusion region. A differential signal (V_(rst)−V_(sig)) is produced bydifferential amplifier 262 for each pixel which is digitized by analogto digital converter 275 (ADC). The analog to digital converter 275supplies the digitized pixel signals to an image processor 280 whichforms a digital image.

FIG. 9 shows a processor system 300, which includes an imager 308constructed in accordance with an embodiment of the invention. Theprocessor system may be part of a digital camera or other imagingsystem. The imager 308 may receive control or other data from system300. System 300 includes a processor 302 having a central processingunit (CPU) for image processing, or other image handling operations. Theprocessor 302 communicates with various devices over a bus 304. Some ofthe devices connected to the bus 304 provide communication into and outof the system 300; an input/output (I/O) device 306 and imager 308 aresuch communication devices. Other devices connected to the bus 304provide memory, for instance, a random access memory (RAM) 310 or aflash memory card 320.

The processor system 300 could alternatively be part of a largerprocessing system, such as a computer. Through the bus 304, theprocessor system 300 illustratively communicates with other computercomponents, including but not limited to, a hard drive 312 and one ormore peripheral memory devices such as a floppy disk drive 314, acompact disk (CD) drive 316.

The processes and devices described above illustrate preferred methodsand typical devices of many that could be used and produced. The abovedescription and drawings illustrate embodiments, which achieve theobjects, features, and advantages of the present invention. However, itis not intended that the present invention be strictly limited to theabove-described and illustrated embodiments. Any modifications, thoughpresently unforeseeable, of the present invention that come within thespirit and scope of the following claims should be considered part ofthe present invention.

1. A semiconductor device structure comprising: a semiconductor substrate having a first surface level; and a photosensor for generating charge in response to light, said photosensor formed at least partially above said first surface level and comprising: a semiconductor layer over said first surface level extending to a second surface level, said semiconductor layer being doped to a first conductivity type; and at least one hydrogenated amorphous silicon layer located above said second surface level, said amorphous silicon layer being doped to a second conductivity type and capable of sensing light.
 2. The semiconductor device of claim 1, wherein said semiconductor layer comprises an epitaxial layer.
 3. The semiconductor device of claim 2, wherein said first conductivity type is p-type.
 4. The semiconductor device of claim 2, wherein said first conductivity type is n-type.
 5. The semiconductor device of claim 2, further comprising a diode region in said substrate.
 6. The semiconductor device of claim 5, wherein said diode is a n-p photodiode.
 7. The semiconductor device of claim 2, wherein said substrate is a p-type doped silicon.
 8. The semiconductor device of claim 2, further comprising a transistor having a gate located adjacent to said epitaxial layer.
 9. The semiconductor device of claim 8, wherein said transistor further comprises at least one oxide spacer in contact with said epitaxial layer.
 10. The semiconductor device of claim 9, wherein said transistor is a transfer transistor.
 11. The semiconductor device of claim 9, wherein said transistor is a reset transistor.
 12. The semiconductor device of claim 2, wherein said at least one hydrogenated amorphous silicon layer comprises two contiguous hydrogenated amorphous silicon layers.
 13. The semiconductor device of claim 12, wherein said second hydrogenated amorphous silicon layer is doped to said first conductivity type.
 14. The semiconductor device of claim 2, wherein said at least one hydrogenated amorphous silicon layer is doped with fluorine.
 15. The semiconductor device of claim 2, wherein said at least one hydrogenated amorphous silicon layer comprises deuterated amorphous silicon.
 16. An imager comprising: a substrate having a first surface level; an array of pixel sensor cells formed in said substrate, wherein each pixel sensor cell has a photosensor comprising doped regions of hydrogenated amorphous silicon, said photosensor at least partially elevated above said first surface level; and signal processing circuitry electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image.
 17. The imager of claim 16, further comprising an epitaxial layer located between said first surface level and said hydrogenated amorphous silicon.
 18. The imager of claim 17, wherein said epitaxial layer is doped p-type.
 19. The imager of claim 18, wherein said hydrogenated amorphous silicon is doped n-type.
 20. The imager of claim 17, wherein said epitaxial layer is located adjacent a transfer transistor.
 21. The imager of claim 20, wherein said epitaxial layer is in contact with an oxided sidewall of said transfer transistor.
 22. The imager of claim 16, wherein each photosensor further comprises a second layer of hydrogenated amorphous silicon formed over said first hydrogenated amorphous silicon layer.
 23. The imager of claim 22, wherein said first and second layers of hydrogenated amorphous silicon further comprise fluorine.
 24. The imager of claim 22, wherein said first and second layers of hydrogenated amorphous silicon further comprise deuterium.
 25. The imager of claim 16, wherein said pixel sensor cells are CMOS cells and said imager is a CMOS imager.
 26. The imager of claim 25, wherein the fill factor of each of said pixel sensor cells is at least fifty percent.
 27. An imager comprising: a substrate having a first surface level; an array of pixel sensor cells formed in said substrate, each pixel sensor cell comprises: a photosensor, for generating charge carriers in response to applied light, said photosensor comprising: a first doped region of a first conductivity type and a second doped region of a second conductivity type, the first doped region located within said substrate and said second doped region located above a first surface level of said substrate; a first hydrogenated amorphous silicon layer located above said first surface level and having a second surface level; and a second hydrogenated amorphous silicon layer located above said second surface level; and at least one transistor formed in said substrate; and signal processing circuitry and electrically connected to the array for receiving and processing signals representing an image output by the array and for providing output data representing said image.
 28. The imager of claim 27, wherein said first and second hydrogenated amorphous silicon layers extend horizontally above the at least one transistor.
 29. The imager of claim 27, wherein said first and second hydrogenated amorphous silicon layers further comprise fluorine.
 30. The imager of claim 27, further comprising a third doped region located within said substrate, said third region doped to said second conductivity type.
 31. The imager of claim 27, wherein said first and second hydrogenated amorphous silicon layers comprise deuterated amorphous silicon layers.
 32. The imager of claim 27, wherein said photosensor is one of a pnp, npn, np, and pn photodiode.
 33. The imager of claim 27, wherein each pixel sensor cell has a fill factor greater than fifty percent.
 34. A processing system comprising: a processor; and an imager coupled to said processor, said imager comprising: a substrate having a first surface level; an array of pixel cells in said substrate, each pixel cell comprising: a photosensor for accumulating photo-generated charge carriers, said photosensor having first and second amorphous silicon layers located above said first surface level and respectively doped to a first and second conductivity type; an epitaxial layer located between said first surface level and said amorphous silicon layers; and a transistor adjacent said epitaxial layer for transferring said generated charge carriers; and a readout circuit comprising at least an output transistor for outputting a signal representing said generated charge carriers.
 35. The system of claim 34, wherein said first and second conductivity types are, respectively, n-type and p type.
 36. The system of claim 34, wherein said epitaxial layer is in contact with an oxide sidewall of said transfer transistor gate.
 37. The system of claim 34, wherein said first and second amorphous silicon layers further comprise fluorine.
 38. The system of claim 34, wherein said first and second amorphous silicon layers comprise deuterated amorphous silicon.
 39. The system of claim 34, wherein said pixel cells are CMOS cells and said imager is a CMOS imager.
 40. A method of forming a photosensor comprising: forming a doped region in a substrate; forming a hydrogenated amorphous silicon layer above a top surface of said doped region of said substrate; and doping said hydrogenated amorphous silicon layer.
 41. The method of claim 40, further comprising the step of growing an epitaxial layer in contact with the top surface of said substrate and beneath said hydrogenated amorphous silicon layer.
 42. The method of claim 41, further comprising the step of planarizing said epitaxial layer to a thickness of about 500 to about 1000 Angstroms.
 43. The method of claim 41, further comprising the step of forming a second hydrogenated amorphous silicon layer above the first hydrogenated amorphous silicon layer.
 44. The method of claim 43, wherein said first amorphous silicon layer has a thickness of about 500 to about 1000 Angstroms.
 45. The method of claim 42, wherein the step of forming a doped region in the substrate comprises forming a pnp photodiode region in the substrate.
 46. The method of claim 45, wherein said epitaxial region is doped n-type.
 47. The method of claim 43, further comprising the step of in situ doping said first and second amorphous silicon layers with fluorine.
 48. The method of claim 43, further comprising the step of implanting fluorine ions in said first and second amorphous silicon layers.
 49. The method of claim 43, further comprising the step of performing an ND3 anneal so that said first and second amorphous silicon layers comprise deuterated amorphous silicon.
 50. A method of forming a pixel sensor cell comprising: providing a substrate; doping a region of said substrate; forming an epitaxial layer above a top surface of said substrate; forming at least one amorphous silicon layer above said epitaxial layer; and forming a transistor comprising a gate stack and an oxide spacer on at least one side of said gate stack and adjacent said epitaxial layer.
 51. The method of claim 50, wherein said step of forming at least one amorphous silicon layer above said epitaxial layer comprises forming two hydrogenated amorphous silicon layers.
 52. The method of claim 50, wherein the step of doping a region of said substrate comprises creating a photodiode region capable of generating charge carriers in response to light.
 53. The method of claim 50, wherein the step of doping a region of said substrate comprises creating one of an n-p-n, n-p or p-n diode region.
 54. The method of claim 51, further comprising the step of doping the first and second hydrogenated amorphous silicon layers as p-type.
 55. The method of claim 51, further comprising the step of doping the first and second hydrogenated amorphous silicon layers as n-type.
 56. The method of claim 51, further comprising the step of respectively doping said first and second amorphous silicon layers as p-type and n-type.
 57. The method of claim 50, wherein said epitaxial layer has a thickness of about 500 to about 1000 Angstroms.
 58. The method of claim 51, further comprising the steps of depositing a buffer layer and patterning an opening in the buffer layer.
 59. The method of claim 58, wherein said buffer layer comprises TEOS.
 60. The method of claim 58, wherein said buffer layer comprises BPSG.
 61. The method of claim 58, wherein said step of forming said first and second amorphous silicon layers comprises depositing amorphous silicon through said opening in said buffer layer.
 62. The method of claim 50, wherein said at least one amorphous silicon layer is hydrogenated.
 63. The method of claim 62, further comprising the step of implanting fluorine ions in said at least one hydrogenated amorphous silicon layer.
 64. The method of claim 62, further comprising the step of performing an ND3 anneal so that said at least one hydrogenated amorphous silicon layer comprises deuterated amorphous silicon.
 65. The method of claim 50, wherein the step of forming an epitaxial layer comprises utilizing a hard mask to selectively deposit said epitaxial layer above said doped region in said substrate.
 66. The method of claim 50, further comprising the step of forming elevated source/drain regions above said top surface of said substrate.
 67. A method of forming a pixel sensor cell having an increased fill factor comprising: providing a substrate; doping at least one region of said substrate, so as to create a diode, said diode having a first surface area; forming at least one hydrogenated amorphous silicon layer above a top surface of said substrate, said at least one hydrogenated amorphous silicon layer extending horizontally above the surface of said substrate and having a second surface area, said second surface area greater than said first surface area; and doping said at least one hydrogenated amorphous silicon layer.
 68. The method of claim 67, wherein said step of forming at least one hydrogenated amorphous silicon layer further comprises forming an epitaxial layer over a top surface of said substrate, said at least one hydrogenated amorphous silicon layer being formed over said epitaxial layer.
 69. The method of claim 67, wherein said step of forming at least one hydrogenated amorphous silicon layer comprises forming a first and a second hydrogenated amorphous silicon layer.
 70. The method of claim 69, further comprising doping said first and second hydrogenated amorphous silicon layers with fluorine ions.
 71. The method of claim 69, further comprising the step of performing an ND3 anneal so that said first and second amorphous silicon layers comprise deuterated amorphous silicon. 